High Level Synthesis of ASICs under Timing and Synchronization Constraints

High Level Synthesis of ASICs under Timing and Synchronization Constraints
Author :
Publisher : Springer Science & Business Media
Total Pages : 302
Release :
ISBN-10 : 9781475721171
ISBN-13 : 147572117X
Rating : 4/5 (17X Downloads)

Book Synopsis High Level Synthesis of ASICs under Timing and Synchronization Constraints by : David C. Ku

Download or read book High Level Synthesis of ASICs under Timing and Synchronization Constraints written by David C. Ku and published by Springer Science & Business Media. This book was released on 2013-03-14 with total page 302 pages. Available in PDF, EPUB and Kindle. Book excerpt: Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.


High Level Synthesis of ASICs under Timing and Synchronization Constraints Related Books

High Level Synthesis of ASICs under Timing and Synchronization Constraints
Language: en
Pages: 302
Authors: David C. Ku
Categories: Technology & Engineering
Type: BOOK - Published: 2013-03-14 - Publisher: Springer Science & Business Media

GET EBOOK

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardwa
High-Level Synthesis for Real-Time Digital Signal Processing
Language: en
Pages: 311
Authors: Jan Vanhoof
Categories: Technology & Engineering
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

GET EBOOK

High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses
SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits
Language: en
Pages: 241
Authors: Sumit Gupta
Categories: Technology & Engineering
Type: BOOK - Published: 2007-05-08 - Publisher: Springer Science & Business Media

GET EBOOK

Rapid advances in microelectronic integration and the advent of Systems-on-Chip have fueled the need for high-level synthesis, i.e., an automated approach to th
Advances in Computers
Language: en
Pages: 469
Authors:
Categories: Computers
Type: BOOK - Published: 1993-09-14 - Publisher: Academic Press

GET EBOOK

Advances in Computers
System-Level Synthesis
Language: en
Pages: 441
Authors: Ahmed Amine Jerraya
Categories: Computers
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

GET EBOOK

System-Level Synthesis deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in