Embedded SoPC Design with Nios II Processor and VHDL Examples

Embedded SoPC Design with Nios II Processor and VHDL Examples
Author :
Publisher : John Wiley & Sons
Total Pages : 728
Release :
ISBN-10 : 9781118008881
ISBN-13 : 111800888X
Rating : 4/5 (88X Downloads)

Book Synopsis Embedded SoPC Design with Nios II Processor and VHDL Examples by : Pong P. Chu

Download or read book Embedded SoPC Design with Nios II Processor and VHDL Examples written by Pong P. Chu and published by John Wiley & Sons. This book was released on 2011-08-29 with total page 728 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology. The book utilizes FPGA devices, Nios II soft-core processor, and development platform from Altera Co., which is one of the two main FPGA manufactures. Altera has a generous university program that provides free software and discounted prototyping boards for educational institutions (details at http://www.altera.com/university). The two main educational prototyping boards are known as DE1 ($99) and DE2 ($269). All experiments can be implemented and tested with these boards. A board combined with this book becomes a “turn-key” solution for the SoPC design experiments and projects. Most HDL and C codes in the book are device independent and can be adapted by other prototyping boards as long as a board has similar I/O configuration.


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